1. Field of the Invention
This invention relates to improvements in integrated circuit testing apparatus or systems, and, more particularly, to a system for testing a plurality of integrated circuits simultaneously in parallel.
2. Description of the Prior Art
In the production of integrated circuits, considerable testing must be done to determine the integrated circuit parameters and whether the integrated circuit performs its intended function. In this regard, comprehensive testing regimens have been developed, the particular regimen used depending, of course, upon the type of integrated circuit being tested and the individual parameters of concern in a particular application. For example, in integrated circuit memories, tests are typically done for determining the speed of the memory. In addition, comprehensive complicated testing routines have been developed, typically to determine whether the memory itself has the capability at each memory address of retaining the memory state desired to be implaced or written into it, under conditions where adjacent cells in each direction containing the same or different state.
In performing the tests, various other testing objectives have been developed. For example, it is often important to identify integrated circuit memories which have a fast access or response time, and separate those memory circuits from other circuits in a common batch to be tested which exhibit slower response times. It is also important in improving production quality that devices exhibiting particular failure modes be isolated so that, for example, if a larger portion of devices in a particular production batch fail for one reason or another, the particular reason in the production process might be identified and cured to improve the overall production quality.
In the past, integrated circuits have usually been tested individually, one at a time. This is particularly time consuming, especially when a large number of tests need to be performed, especially in consideration of the ever increasing complexity and size of devices to be tested. For example, a simple 16K random access memory (RAM) takes about 12 to 24 seconds, or even more, to test, even with the test signals generated and applied by a computer. It will be appreciated that larger sized memories (and other complex integrated circuits) would take even larger times for testing. The state of the art presently is experiencing the production of larger memories in the range of 256K or more, requiring sometimes minutes to complete the comprehensive required testing.
It has been suggested in the past to parallel test integrated circuits, but such efforts have been unsuccessful, and economically impractical, primarily because the testing apparatuses which have been used were completely parallel, that is, with both the inputs and the outputs being respectively connected in parallel. Thus, the prior apparatuses tend to average the output consequently, a failed device could not be detected by an average which was out of range. The best that could be accomplished or determined was that one device in a set of devices under test failed, but the particular failed device could not be isolated from the rest. In addition, no one has accomplished parametric testing of devices.
A suggestion of parallel functional testing has been made by J. D. Lawrence, Parallel Test With Burn-In For Enhanced Quality and Reliability, Microelectronic Manufacturing and Testing, pp 22 et seq., January, 1982. It should be noted particularly that parametric testing is performed serially.